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september 8, 2004 ? cypress microsystems, inc. 2004 ? document no. 38-12028 rev. *b 1 psoc? mixed-signal array final data sheet cy8c24123a, cy8c24223a, and cy8c24423a psoc? functional overview the psoc? family consists of many mixed-signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of conve- nient pinouts and packages. the psoc architecture, as illustrated on the left, is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows all the device resources to be combined into a complete custom system. the psoc cy8c24x23a family can have up to three io ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. the psoc core the psoc core is a powerful engine that supports a rich fea- ture set. the core includes a cpu, memory, clocks, and config- urable gpio (gene ral purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? 8x8 multiply, 32-bit accumulate ? low power at high speed ? 2.4 to 5.25 v operating voltage ? operating voltages down to 1.0v using on- chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 6 rail-to-rail analog psoc blocks provide: - up to 14-bit adcs - up to 9-bit dacs - programmable gain amplifiers - programmable filters and comparators ? 4 digital psoc blocks provide: - 8- to 32-bit timers, counters, and pwms - crc and prs modules - full-duplex uart - multiple spi ? masters or slaves - connectable to all gpio pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? high-accuracy 24 mhz with optional 32 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 4k bytes flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 10 analog inputs on gpio ? two 30 ma analog outputs on gpio ? configurable interrupt on all gpio new cy8c24x23a psoc device ? derived from the cy8c24x23 device ? low power and low voltage (2.4v) additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 4k digital block array multiply accum. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input muxing i 2 c (1 row, 4 blocks) port 2 port 1 port 0 analog drivers system bus analog block array (2 columns, 6 blocks)
september 8, 2004 document no. 38-12028 rev. *b 2 cy8c24x23a final data sheet psoc? overview processor. the cpu utilizes an interrupt controller with 11 vec- tors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 4 kb of flash for program storage, 256 bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock genera- tors, including a 24 mhz imo (internal main oscillator) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crys- tal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfac- ing. every pin also has the capability to generate a system inter- rupt on high level, low level, and change from last read. the digital system the digital system is composed of 4 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital system block diagram digital peripheral configurations include those listed below. pwms (8 to 32 bit) pwms with dead band (8 to 24 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master (1 available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to 1) pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the con- straints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the opti- mum choice of system resources for your application. family resources are shown in the table titled ?psoc device charac- teristics? on page 3 . the analog system the analog system is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common psoc analog functions (most avail- able as user modules) are listed below. analog-to-digital converters (up to 2, with 6- to 14-bit resolu- tion, selectable as incremental, delta sigma, and sar) filters (2 and 4 pole band-pass, low-pass, and notch) amplifiers (up to 2, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to 2, with 16 selectable thresholds) dacs (up to 2, with 6- to 9-bit resolution) multiplying dacs (up to 2, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0
september 8, 2004 document no. 38-12028 rev. *b 3 cy8c24x23a final data sheet psoc? overview analog blocks are arranged in a column of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown in the figure below. analog system block diagram additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. addi- tional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. brief state- ments describing the merits of each system resource are pre- sented below. digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following table lists the resources available for specific psoc device groups. the psoc device covered by this data sheet is shown in the next to the last row of the table. acb00 acb01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandga p refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference psoc device characteristics psoc device group digital io (max) digital rows digital blocks analog inputs analog outputs analog columns analog blocks amount of sram amount of flash cy8c29x66 64 4 16 12 4 4 12 2 kb 32 kb cy8c27x43 44 2 8 12 4 4 12 256 bytes 16 kb cy8c24x23 24 1 4 12 2 2 6 256 bytes 4 kb cy8c24x23a 24 1 4 12 2 2 6 256 bytes 4 kb cy8c22x13 16 1 4 8 1 1 3 256 bytes 2 kb cy8c21x34 28 1 4 28 0 2 4 a a. limited analog functionality. 512 bytes 8 kb cy8c21x23 16 1 4 8 0 2 4 a 256 bytes 4 kb
september 8, 2004 document no. 38-12028 rev. *b 4 cy8c24x23a final data sheet psoc? overview getting started the quickest path to understanding the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc? mixed signal array technical reference manual . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com/psoc. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store at http://www.onfulfillment.com/cypressstore/ contains develop- ment kits, c compilers, and all accessories for psoc develop- ment. click on psoc (programmable system-on-chip) to view a current list of available items. tele-training free psoc "tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes cover- ing topics like psoc and the lin bus. for days and times of the tele-training, see http://www.cypress.com/support/training.cfm . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to the following cypress support web site: http://www.cypress.com/support/cypros.cfm . technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to locate the psoc application notes, go to http://www.cypress.com/design/results.cfm . development tools the cypress microsystems psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, win- dows 2000, windows millennium (me), or windows xp. (refer- ence the psoc designer functional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc tm designer
september 8, 2004 document no. 38-12028 rev. *b 5 cy8c24x23a final data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configu- ration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports cypress microsystems? psoc family devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of the parallel or usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation.
september 8, 2004 document no. 38-12028 rev. *b 6 cy8c24x23a final data sheet psoc? overview user module development process the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library con- tains over 50 common peripherals such as adcs, dacs tim- ers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service rou- tines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the set- ting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. user module and source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the hex image to the in-circuit emulator (ice) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter- ization generate application build all event & breakpoint manager build manager source code generator
september 8, 2004 document no. 38-12028 rev. *b 7 cy8c24x23a final data sheet psoc? overview document conventions acronyms used the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 3-1 on page 15 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed signal array technical refer- ence manual . this document encompasses and is organized into the following chapters and sections. 1. pin information ............................................................. 8 1.1 pinouts ................................................................... 8 1.1.1 8-pin part pinout ........................................ 8 1.1.2 20-pin part pinout ...................................... 9 1.1.3 28-pin part pinout .................................... 10 1.1.4 32-pin part pinout .................................... 11 2. register reference ..................................................... 12 2.1 register conventions ........................................... 12 2.1.1 abbreviations used .................................. 12 2.2 register mapping tables ..................................... 12 3. electrical specifications ............................................ 15 3.1 absolute maximum ratings ................................ 16 3.2 operating temperature ....................................... 16 3.3 dc electrical characteristics ................................ 17 3.3.1 dc chip-level specifications ................... 17 3.3.2 dc general purpose io specifications .... 18 3.3.3 dc operational amplifier specifications ... 19 3.3.4 dc analog output buffer specifications ... 22 3.3.5 dc switch mode pump specifications ..... 24 3.3.6 dc analog reference specifications ....... 25 3.3.7 dc analog psoc block specifications ..... 26 3.3.8 dc por, smp, and lvd specifications ... 27 3.3.9 dc programming specifications ............... 28 3.4 ac electrical characteristics ................................ 29 3.4.1 ac chip-level specifications ................... 29 3.4.2 ac general purpose io specifications .... 32 3.4.3 ac operational amplifier specifications ... 33 3.4.4 ac digital block specifications ................. 34 3.4.5 ac analog output buffer specifications ... 36 3.4.6 ac external clock specifications ............. 37 3.4.7 ac programming specifications ............... 38 3.4.8 ac i2c specifications ............................... 39 4. packaging information ............................................... 40 4.1 packaging dimensions ......................................... 40 4.2 thermal impedances .......................................... 45 4.3 capacitance on crystal pins ............................... 45 5. ordering information .................................................. 46 5.1 ordering code definitions .................................... 46 6. sales and company information ............................... 47 6.1 revision history ................................................... 47 6.2 copyrights and code protection .......................... 47 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory
september 8, 2004 document no. 38-12028 rev. *b 8 1. pin information this chapter describes, lists, and illustrates the cy8c24x23a psoc device pins and pinout configurations. 1.1 pinouts the cy8c24x23a psoc device is available in a variety of packages which are listed and illustrated in the following tables. ever y port pin (labeled with a ?p?) is capable of digital io. however, vss, vdd, smp, and xres are not capable of digital io. 1.1.1 8-pin part pinout table 1-1. 8-pin part pinout (pdip, soic) pin no. type pin name description cy8c24123a 8-pin psoc device digital analog 1 io io p0[5] analog column mux input and column output. 2 io io p0[3] analog column mux input and column output. 3 io p1[1] crystal input (xtalin), i2c serial clock (scl) 4 power vss ground connection. 5 io p1[0] crystal output (xtalout), i2c serial data (sda) 6 io i p0[2] analog column mux input. 7 io i p0[4] analog column mux input. 8 power vdd supply voltage. legend : a = analog, i = input, and o = output. pdip soic 1 2 3 4 8 7 6 5 vdd p0[4], ai p0[2], ai p1[0], xtalout, i2c sd a aio, p0[5] aio, p0[3] i2c scl, xtalin, p1[1] vss
september 8, 2004 document no. 38-12028 rev. *b 9 cy8c24x23a final data sheet 1. pin information 1.1.2 20-pin part pinout table 1-2. 20-pin part pinout (pdip, ssop, soic) pin no. type pin name description cy8c24223a 20-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 power smp switch mode pump (smp) connection to external components required. 6 io p1[7] i2c serial clock (scl) 7 io p1[5] i2c serial data (sda) 8 io p1[3] 9 io p1[1] crystal input (xtalin), i2c serial clock (scl) 10 power vss ground connection. 11 io p1[0] crystal output (xtalout), i2c serial data (sda) 12 io p1[2] 13 io p1[4] optional external clock input (extclk) 14 io p1[6] 15 input xres active high external reset with internal pull down. 16 io i p0[0] analog column mux input. 17 io i p0[2] analog column mux input. 18 io i p0[4] analog column mux input. 19 io i p0[6] analog column mux input. 20 power vdd supply voltage. legend : a = analog, i = input, and o = output. ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss pdip ssop soic 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vdd p0[6], ai p0[4], ai p0[2], ai p0[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sd a
september 8, 2004 document no. 38-12028 rev. *b 10 cy8c24x23a final data sheet 1. pin information 1.1.3 28-pin part pinout table 1-3. 28-pin part pinout (pdip, ssop, soic) pin no. type pin name description cy8c24423a 28-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 power smp switch mode pump (smp) connection to external components required. 10 io p1[7] i2c serial clock (scl) 11 io p1[5] i2c serial data (sda) 12 io p1[3] 13 io p1[1] crystal input (xtalin), i2c serial clock (scl) 14 power vss ground connection. 15 io p1[0] crystal output (xtalout), i2c serial data (sda) 16 io p1[2] 17 io p1[4] optional external clock input (extclk) 18 io p1[6] 19 input xres active high external reset with internal pull down. 20 io i p2[0] direct switched capacitor block input. 21 io i p2[2] direct switched capacitor block input. 22 io p2[4] external analog ground (agnd) 23 io p2[6] external voltage reference (vref) 24 io i p0[0] analog column mux input. 25 io i p0[2] analog column mux input. 26 io i p0[4] analog column mux input. 27 io i p0[6] analog column mux input. 28 power vdd supply voltage. legend : a = analog, i = input, and o = output. ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], ai p0[4], ai p0[2], ai p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sd a pdip ssop soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
september 8, 2004 document no. 38-12028 rev. *b 11 cy8c24x23a final data sheet 1. pin information 1.1.4 32-pin part pinout table 1-4. 32-pin part pinout (mlf*) pin no. type pin name description cy8c24423a 32-pin psoc device digital analog 1 io p2[7] 2 io p2[5] 3 io i p2[3] direct switched capacitor block input. 4 io i p2[1] direct switched capacitor block input. 5 power vss ground connection. 6 power smp switch mode pump (smp) connection to external components required. 7 io p1[7] i2c serial clock (scl) 8 io p1[5] i2c serial data (sda) 9 nc no connection. do not use. 10 io p1[3] 11 io p1[1] crystal input (xtalin), i2c serial clock (scl) 12 power vss ground connection. 13 io p1[0] crystal output (xtalout), i2c serial data (sda) 14 io p1[2] 15 io p1[4] optional external clock input (extclk) 16 nc no connection. do not use. 17 io p1[6] 18 input xres active high external reset with internal pull down. 19 io i p2[0] direct switched capacitor block input. 20 io i p2[2] direct switched capacitor block input. 21 io p2[4] external analog ground (agnd) 22 io p2[6] external voltage reference (vref) 23 io i p0[0] analog column mux input. 24 io i p0[2] analog column mux input. 25 nc no connection. do not use. 26 io i p0[4] analog column mux input. 27 io i p0[6] analog column mux input. 28 power vdd supply voltage. 29 io i p0[7] analog column mux input. 30 io io p0[5] analog column mux input and column output. 31 io io p0[3] analog column mux input and column output. 32 io i p0[1] analog column mux input. legend : a = analog, i = input, and o = output. * the mlf package has a center pad that must be connected to ground (vss). p2[7] p2[5] ai, p2[3] ai, p2[1] vss smp mlf (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 p0[1], ai p0[3], ai o p0[5], ai o p0[7], ai vdd p0[6], ai p0[4], ai nc i2c scl, p1[7] i 2c sda, p1[5] p0[2], ai p0[0], ai xres p1[6] nc p1[3] i2c scl, xtalin, p1[1] vss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] nc p2[6], external vre f p2[4], external agn d p2[2], ai p2[0], ai
september 8, 2004 document no. 38-12028 rev. *b 12 2. register reference this chapter lists the registers of the cy8c24x23a psoc device. for detailed register information, reference the psoc? mixed sig- nal array technical reference manual . 2.1 register conventions 2.1.1 abbreviations used the register conventions specific to this section are listed in the following table. 2.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
september 8, 2004 document no. 38-12028 rev. *b 13 cy8c24x23a final data sheet 2. register reference register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw d0 11 51 asd20cr1 91 rw d1 12 52 asd20cr2 92 rw d2 13 53 asd20cr3 93 rw d3 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw i2c_cfg d6 rw 17 57 asc21cr3 97 rw i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul_x e8 w dcb02dr1 29 w 69 a9 mul_y e9 w dcb02dr2 2a rw 6a aa mul_dh ea r dcb02cr0 2b # 6b ab mul_dl eb r dcb03dr0 2c # 6c ac acc_dr1 ec rw dcb03dr1 2d w 6d ad acc_dr0 ed rw dcb03dr2 2e rw 6e ae acc_dr3 ee rw dcb03cr0 2f # 6f af acc_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
september 8, 2004 document no. 38-12028 rev. *b 14 cy8c24x23a final data sheet 2. register reference register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw c0 prt0dm1 01 rw 41 asc10cr1 81 rw c1 prt0ic0 02 rw 42 asc10cr2 82 rw c2 prt0ic1 03 rw 43 asc10cr3 83 rw c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw gdi_o_in d0 rw 11 51 asd20cr1 91 rw gdi_e_in d1 rw 12 52 asd20cr2 92 rw gdi_o_ou d2 rw 13 53 asd20cr3 93 rw gdi_e_ou d3 rw 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw d6 17 57 asc21cr3 97 rw d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw 6c ac ec dcb03in 2d rw 6d ad ed dcb03ou 2e rw 6e ae ee 2f 6f af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
september 8, 2004 document no. 38-12028 rev. *b 15 3. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c24x23a psoc device. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. specifications for devices running at greater than 12 mhz are valid for -40 o c t a 70 o c and t j 82 o c. refer to table 3-20 for the electrical specifications on the internal main oscillator (imo) using slimo mode. figure 3-1a. voltage versus cpu frequency figure 3-1b. imo frequency trim options the following table lists the units of measure that are used in this chapter. table 3-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w micro watts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nano ampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa pico ampere m ? megaohm pf pico farad a micro ampere pp peak-to-peak f micro farad ppm parts per million h micro henry ps picosecond s microsecond sps samples per second v micro volts sigma: one standard deviation vrms micro volts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0
september 8, 2004 document no. 38-12028 rev. *b 16 cy8c24x23a final data sheet 3. electrical specifications 3.1 absolute maximum ratings 3.2 operating temperature table 3-2. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 o c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma table 3-3. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 45 . the user must limit the power con- sumption to comply with this requirement.
september 8, 2004 document no. 38-12028 rev. *b 17 cy8c24x23a final data sheet 3. electrical specifications 3.3 dc electrical characteristics 3.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-4. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.4 ? 5.25 v see dc por and lvd specifications, ta b l e 3 - 18 on page 27 . i dd supply current ? 5 8 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, ana- log power = off. i dd3 supply current ? 3.3 6.0 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, ana- log power = off. i dd27 supply current when imo = 6 mhz using slimo mode. ? 2 4 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 0.75 mhz, 48 mhz = disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz, analog power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. a a. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled. ? 3 6.5 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, -40 o c t a 55 o c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. a ? 4 25 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, 55 o c < t a 85 o c, analog power = off. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. a ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40 o c t a 55 o c, analog power = off. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. a ? 5 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3 v, 55 o c < t a 85 o c, analog power = off. v ref reference voltage (bandgap) 1.28 1.30 1.33 v trimmed for appropriate vdd. vdd > 3.0v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v.
september 8, 2004 document no. 38-12028 rev. *b 18 cy8c24x23a final data sheet 3. electrical specifications 3.3.2 dc general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-5. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k ? r pd pull down resistor 4 5.6 8 k ? v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (maximum 40 ma on even port pins (for example, p0[2], p1[4]), maximum 40 ma on odd port pins (for example, p0[3], p1[5])). 80 ma maximum com- bined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (maximum 100 ma on even port pins (for example, p0[2], p1[4]), maximum 100 ma on odd port pins (for example, p0[3], p1[5])). 150 ma maximum com- bined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. table 3-6. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k ? r pd pull down resistor 4 5.6 8 k ? v oh high output level vdd - 0.4 ? ? v ioh = 2 ma (6.25 typ), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined ioh bud- get). v ol low output level ? ? 0.75 v iol = 11.25 ma, vdd = 2.4 to 3.0v (90 ma max- imum combined iol budget). v il input low level ? ? 0.8 v vdd = 2.4 to 3.0 v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0 v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c.
september 8, 2004 document no. 38-12028 rev. *b 19 cy8c24x23a final data sheet 3. electrical specifications 3.3.3 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched cap psoc blocks. the guaranteed specifications are measured in the analog continuous time psoc block. typical parameters apply to 5v at 25 c and are for design guidance only. table 3-7. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is mea- sured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = high power = low, opamp bias = high power = medium, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 64 ? ? db 0v v in (vdd - 2.30) or (vdd - 1.25v) v in vdd .
september 8, 2004 document no. 38-12028 rev. *b 20 cy8c24x23a final data sheet 3. electrical specifications table 3-8. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 64 ? ? db 0v v in (vdd - 2.30) or (vdd - 1.25v) v in vdd .
september 8, 2004 document no. 38-12028 rev. *b 21 cy8c24x23a final data sheet 3. electrical specifications table 3-9. 2.7v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 64 ? ? db 0v v in (vdd - 2.30) or (vdd - 1.25v) v in vdd .
september 8, 2004 document no. 38-12028 rev. *b 22 cy8c24x23a final data sheet 3. electrical specifications 3.3.4 dc analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-10. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.1 0.5 x vdd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 ? ? db v out > (vdd - 1.25) table 3-11. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 ? ? db v out > (vdd - 1.25)
september 8, 2004 document no. 38-12028 rev. *b 23 cy8c24x23a final data sheet 3. electrical specifications table 3-12. 2.7v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 0.2 0.5 x vdd + 0.2 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 0.7 0.5 x vdd - 0.7 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 ? ? db v out > (vdd - 1.25)
september 8, 2004 document no. 38-12028 rev. *b 24 cy8c24x23a final data sheet 3. electrical specifications 3.3.5 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. figure 3-2. basic switch mode pump circuit table 3-13. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5v 5v output voltage from pump 4.75 5.0 5.25 v configuration of footnote a . average, neglecting ripple. smp trip voltage is set to 5.0v. v pump 3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote a . average, neglecting ripple. smp trip voltage is set to 3.25v. v pump 2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote a . average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.8v, v pump = 5.0v v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote a . smp trip voltage is set to 5.0v. smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat 5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote a . smp trip voltage is set to 5.0v. v bat 3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote a . smp trip voltage is set to 3.25v. v bat 2v input voltage range from battery 1.0 ? 3.0 v configuration of footnote a . smp trip voltage is set to 2.55v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote a . 0 o c t a 100. 1.25v at t a = -40 o c. ? v pump_line line regulation (over v bat range) ? 5 ? %v o configuration of footnote a . v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3-18 on page 27 . ? v pump_load load regulation ? 5 ? %v o configuration of footnote a . v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3-18 on page 27 . ? v pump_ripple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configuration of footnote a . load is 5 ma. a. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 3-2. e 3 efficiency 35 50 ? % configuration of footnote a . load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % battery c1 d1 + psoc tm vdd vss smp v bat l 1 v pum p
september 8, 2004 document no. 38-12028 rev. *b 25 cy8c24x23a final data sheet 3. electrical specifications 3.3.6 dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the guaranteed specifications are measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 3-14. 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.33 v ? agnd = vdd/2 vdd/2 - 0.04 vdd/2 - 0.01 vdd/2 + 0.007 v ? agnd = 2 x bandgap 2 x bg - 0.048 2 x bg - 0.030 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap bg - 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap 1.6 x bg - 0.022 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + bg - 0.10 vdd /2 + bg vdd /2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg - 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.113 2 x bg + p2[6] - 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6]+ 0.100 v ? refhi = 3.2 x bandgap 3.2 x bg - 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd /2 - bg - 0.04 vdd /2 - bg + 0.024 vdd /2 - bg + 0.04 v ? reflo = bandgap bg - 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 3-15. 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.33 v ? agnd = vdd/2 vdd/2 - 0.03 vdd/2 - 0.01 vdd/2 + 0.005 v ? agnd = 2 x bandgap not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap bg - 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap 1.6 x bg - 0.027 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = vdd/2) -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.075 p2[4] + p2[6] - 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4]- p2[6] + 0.022 p2[4] - p2[6] + 0.092 v
september 8, 2004 document no. 38-12028 rev. *b 26 cy8c24x23a final data sheet 3. electrical specifications 3.3.7 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-16. 2.7v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.16 1.30 1.33 v ? agnd = vdd/2 vdd/2 - 0.03 vdd/2 - 0.01 vdd/2 + 0.01 v ? agnd = 2 x bandgap not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.01 p2[4] p2[4] + 0.01 v ? agnd = bandgap bg - 0.01 bg bg + 0.015 v ? agnd = 1.6 x bandgap not allowed ? agnd column to column variation (agnd = vdd/2) -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.08 p2[4] + p2[6] - 0.01 p2[4] + p2[6] + 0.06 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.05 p2[4]- p2[6] + 0.01 p2[4] - p2[6] + 0.09 v table 3-17. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switch cap) ? 80 ? ff
september 8, 2004 document no. 38-12028 rev. *b 27 cy8c24x23a final data sheet 3. electrical specifications 3.3.8 dc por, smp, and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc mixed signal array technical reference manual for more information on the vlt_cr register. table 3-18. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lv d0 v lv d1 v lv d2 v lv d3 v lv d4 v lv d5 v lv d6 v lv d7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 0 2.92 0 3.02 3.13 4.48 4.64 4.73 4.81 2.51 a 2.99 b 3.09 3.20 4.55 4.75 4.83 4.95 a. always greater than 50 mv above v ppor (porlev=00) for falling supply. b. always greater than 50 mv above v ppor (porlev=01) for falling supply. v 0 v 0 v 0 v 0 v 0 v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for smp trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.50 0 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 0 3.02 3.10 3.25 0 4.64 4.73 4.82 5.00 2.62 c 3.09 3.16 3.32 d 4.74 4.83 4.92 5.12 c. always greater than 50 mv above v lvd0 . d. always greater than 50 mv above v lvd3 . v v 0 v 0 v 0 v 0 v v v
september 8, 2004 document no. 38-12028 rev. *b 28 cy8c24x23a final data sheet 3. electrical specifications 3.3.9 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-19. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years
september 8, 2004 document no. 38-12028 rev. *b 29 cy8c24x23a final data sheet 3. electrical specifications 3.4 ac electrical characteristics 3.4.1 ac chip-level specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-20. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 a,b,c mhz trimmed for 5v or 3.3v operation using fac- tory trim values. see figure 3-1b on page 15 . slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 5v or 3.3v operation using fac- tory trim values. see figure 3-1b on page 15 . slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b,c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. mhz f 48m digital psoc block frequency 0 48 49.2 a,b,d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz refer to the ac digital block specifications below. f 24m digital psoc block frequency 0 24 24.6 b, d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz is a multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms t pllslews- low pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a prop- erly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0v vdd 5.5v, -40 o c t a 85 o c. jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. utilizing factory trim values. jitter24m1p 24 mhz period jitter (imo) peak-to-peak ? 300 ps jitter24m1r 24 mhz period jitter (imo) root mean squared ? ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s
september 8, 2004 document no. 38-12028 rev. *b 30 cy8c24x23a final data sheet 3. electrical specifications figure 3-3. pll lock timing diagram figure 3-4. pll lock for low gain setting timing diagram table 3-21. 2.7v ac chip-level specifications symbol description min typ max units notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 12.7 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0 0.93 0 3 0 3.15 a,b mhz 0 f blk27 digital psoc block frequency (2.7v nominal) 0 12 12.7 a,b,c mhz 0 refer to the ac digital block specifica- tions below. f 32k1 internal low speed oscillator frequency 8 32 96 khz jitter32k 32 khz period jitter ? 150 ns t xrst external reset pulse width 10 ? ? s dc12m 12 mhz duty cycle 40 50 60 % jitter12m1p 12 mhz period jitter (imo) peak-to-peak ? 340 ps jitter12m1r 12 mhz period jitter (imo) root mean squared ? ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.7 mhz t ramp supply ramp time 0 ? ? s a. 2.4v < vdd < 3.0v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. c. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on maximu m frequency for user modules. 24 mhz f pll pll e nable t pllslew pll gain 0 24 mhz f pll pll e nable t pllslewlow pll gain 1
september 8, 2004 document no. 38-12028 rev. *b 31 cy8c24x23a final data sheet 3. electrical specifications figure 3-5. external crystal oscillator startup timing diagram figure 3-6. 24 mhz period jitter (imo) timing diagram figure 3-7. 32 khz period jitter (eco) timing diagram 32 khz f 32k2 32k s elect t os jitter24m1 f 24m jitter32k f 32k2
september 8, 2004 document no. 38-12028 rev. *b 32 cy8c24x23a final data sheet 3. electrical specifications 3.4.2 ac general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. figure 3-8. gpio timing diagram table 3-22. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 3-23. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin output v oltage
september 8, 2004 document no. 38-12028 rev. *b 33 cy8c24x23a final data sheet 3. electrical specifications 3.4.3 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v and 2.7v. table 3-24. 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 3-25. 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
september 8, 2004 document no. 38-12028 rev. *b 34 cy8c24x23a final data sheet 3. electrical specifications 3.4.4 ac digital block specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-26. 2.7v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 3-27. 5v and 3.3v ac digital block specifications function description min typ max units notes timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 24.6 mhz counter enable pulse width 50 a ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 ns width of ss_ negated between transmissions 50 a ? ? ns transmitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking.
september 8, 2004 document no. 38-12028 rev. *b 35 cy8c24x23a final data sheet 3. electrical specifications table 3-28. 2.7v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). ? 0 ? 0 ns maximum frequency, with or without capture ? ? 12.7 mhz counter enable pulse width 100 a ? 0 ? 0 ns maximum frequency, no enable input ? ? 12.7 mhz maximum frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 a ? 0 ? 0 ns disable mode 0 100 a ? 0 ? 0 ns maximum frequency ? ? 12.7 mhz crcprs (prs mode) maximum input clock frequency ? ? 12.7 mhz crcprs (crc mode) maximum input clock frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.23 ns width of ss_ negated between transmissions 100 a ? 0 ? 0 ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking.
september 8, 2004 document no. 38-12028 rev. *b 36 cy8c24x23a final data sheet 3. electrical specifications 3.4.5 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-29. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 3-30. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz
september 8, 2004 document no. 38-12028 rev. *b 37 cy8c24x23a final data sheet 3. electrical specifications 3.4.6 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-31. 2.7v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3 3 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.4 0.4 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.4 0.4 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.6 0.6 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 180 180 ? ? ? ? khz khz table 3-32. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 3-33. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 a a. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum f requency and duty cycle requirements. 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater b b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this cas e, the cpu clock divider will ensure that the fifty per- cent duty cycle requirement is met. 0.186 ?24.6mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s
september 8, 2004 document no. 38-12028 rev. *b 38 cy8c24x23a final data sheet 3. electrical specifications 3.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-34. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 a 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater b 0.186 ?12.3mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s a. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum f requency and duty cycle requirements. b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this cas e, the cpu clock divider will ensure that the fifty per- cent duty cycle requirement is met. table 3-35. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 20 ? ms t write flash block write time ? 20 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0
september 8, 2004 document no. 38-12028 rev. *b 39 cy8c24x23a final data sheet 3. electrical specifications 3.4.8 ac i 2 c specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. figure 3-9. definition for timing for fast/standard mode on the i 2 c bus table 3-36. ac characteristics of the i 2 c sda and scl pins for vdd > 3.0v symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns table 3-37. ac characteristics of the i 2 c sda and scl pins for vdd < 3.0v (fast mode not supported) symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 ? ?khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c set-up time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set-up time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ? ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? ? ?ns s da scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
september 8, 2004 document no. 38-12028 rev. *b 40 4. packaging information this chapter illustrates the packaging specifications for the cy8c24x23a psoc device, along with the thermal impedances for eac h package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim . 4.1 packaging dimensions figure 4-1. 8-lead (300-mil) pdip 51-85075 - *a
september 8, 2004 document no. 38-12028 rev. *b 41 cy8c24x23a final data sheet 4. packaging information figure 4-2. 8-lead (150-mil) soic figure 4-3. 20-lead (300-mil) molded dip 51-85066 *b 51-85066 - *c 51-85011-a 20-lead (300-mil) molded dipp5 51-85011 - *a
september 8, 2004 document no. 38-12028 rev. *b 42 cy8c24x23a final data sheet 4. packaging information figure 4-4. 20-lead (210-mil) ssop figure 4-5. 20-lead (300-mil) molded soic 51-85077 - *c 51-85024 - *b
september 8, 2004 document no. 38-12028 rev. *b 43 cy8c24x23a final data sheet 4. packaging information figure 4-6. 28-lead (300-mil) molded dip figure 4-7. 28-lead (210-mil) ssop 51-85014 - *d 51-85079 - *c
september 8, 2004 document no. 38-12028 rev. *b 44 cy8c24x23a final data sheet 4. packaging information figure 4-8. 28-lead (300-mil) molded soic figure 4-9. 32-lead (5x5 mm) mlf 51-85026 - *c 51-85188 - ** 32 x = 138 mil y = 138 mil
september 8, 2004 document no. 38-12028 rev. *b 45 cy8c24x23a final data sheet 4. packaging information 4.2 thermal impedances 4.3 capacitance on crystal pins table 4-1. thermal impedances per package package typical ja * 8 pdip 123 o c/w 8 soic 185 o c/w 20 pdip 109 o c/w 20 ssop 117 o c/w 20 soic 81 o c/w 28 pdip 69 o c/w 28 ssop 101 o c/w 28 soic 74 o c/w 32 mlf 22 o c/w * t j = t a + power x ja table 4-2: typical package capacitance on crystal pins package package capacitance 8 pdip 2.8 pf 8 soic 2.0 pf 20 pdip 3.0 pf 20 ssop 2.6 pf 20 soic 2.5 pf 28 pdip 3.5 pf 28 ssop 2.8 pf 28 soic 2.7 pf 32 mlf 2.0 pf
september 8, 2004 document no. 38-12028 rev. *b 46 5. ordering information the following table lists the cy8c24x23a psoc device family?s key package features and ordering codes. 5.1 ordering code definitions table 5-1. cy8c24x23a psoc device key features and ordering information package ordering code flash (kbytes) ram (bytes) switch mode pump temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital io pins analog inputs analog outputs xres pin 8 pin (300 mil) dip cy8c24123a-24pxi 4 256 no -40c to +85c 4 6 6 4 2 no 8 pin (150 mil) soic cy8c24123a-24sxi 4 256 yes -40c to +85c 4 6 6 4 2 no 8 pin (150 mil) soic (tape and reel) cy8c24123a-24sxit 4 256 yes -40c to +85c 4 6 6 4 2 no 20 pin (300 mil) dip cy8c24223a-24pxi 4 256 yes -40c to +85c 4 6 16 8 2 yes 20 pin (210 mil) ssop cy8c24223a-24pvxi 4 256 yes -40c to +85c 4 6 16 8 2 yes 20 pin (210 mil) ssop (tape and reel) cy8c24223a-24pvxit 4 256 yes -40c to +85c 4 6 16 8 2 yes 20 pin (300 mil) soic cy8c24223a-24sxi 4 256 yes -40c to +85c 4 6 16 8 2 yes 20 pin (300 mil) soic (tape and reel) cy8c24223a-24sxit 4 256 yes -40c to +85c 4 6 16 8 2 yes 28 pin (300 mil) dip cy8c24423a-24pxi 4 256 yes -40c to +85c 4 6 24 10 2 yes 28 pin (210 mil) ssop cy8c24423a-24pvxi 4 256 yes -40c to +85c 4 6 24 10 2 yes 28 pin (210 mil) ssop (tape and reel) cy8c24423a-24pvxit 4 256 yes -40c to +85c 4 6 24 10 2 yes 28 pin (300 mil) soic cy8c24423a-24sxi 4 256 yes -40c to +85c 4 6 24 10 2 yes 28 pin (300 mil) soic (tape and reel) cy8c24423a-24sxit 4 256 yes -40c to +85c 4 6 24 10 2 yes 32 pin (5x5 mm) mlf CY8C24423A-24LFXI 4 256 yes -40c to +85c 4 6 24 10 2 yes cy 8 c 24 xxx-spxx package type: thermal rating: px = pdip pb free c = commercial sx = soic pb free i = industrial pvx = ssop pb free e = extended lfx = mlf pb free ax = tqfp pb free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress
september 8, 2004 ? cypress microsystems, inc. 2004 ? document no. 38-12028 rev. *b 47 6. sales and company information to obtain information about cypress microsystems or psoc sales and technical support, reference the following information or go to the section titled ?getting started? on page 4 in this document. cypress microsystems 6.1 revision history 6.2 copyrights and code protection copyrights ? cypress microsystems, inc. 2004. all rights reserved. psoc?, psoc designer?, and programmable system-on-chip? are trademarks of cypress microsystems, inc. all other trademarks or registered trademarks referenced herein are property of the respective corporations. the information contained herein is subject to change without notice. cypress microsystems assumes no responsibility for the us e of any circuitry other than circuitry embodied in a cypress microsystems product. nor does it convey or imply any license under patent or other rights. cypress micro systems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress microsystems products in life-support systems application implies that the manufacturer assumes all risk of such use an d in doing so indemnifies cypress microsystems against all charges. cypress microsystems products are not warranted nor intended to be used for medical, life-sup port, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress microsystems. flash code protection note the following details of the flash code protection features on cypress microsystems devices. cypress microsystems products meet the specifications contained in their particular cypress microsystems data sheets. cypress m icrosystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be meth ods, unknown to cypress microsystems, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress microsystems nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteei ng the product as "unbreakable." cypress microsystems is willing to work with the customer who is concerned about the integrity of their code. code protection i s constantly evolving. we at cypress micro- systems are committed to continuously improvin g the code protection features of our products. 2700 162nd street sw building d lynnwood, wa 98037 phone: 800.669.0557 facsimile: 425.787.4641 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm table 6-1. cy8c24x23a data sheet revision history document title: cy8c24123a, cy8c24223a, and cy8c24423a psoc mixed signal array final data sheet document number: 38-12028 revision ecn # issue date origin of change description of change ** 236409 see ecn sfv new silicon and new document ? preliminary data sheet. *a 247589 see ecn sfv changed the title to read ?final? data sheet. updated electrical specifications chapter. *b 261711 see ecn hmt input all sfv memo changes. updated electrical specifications chapter. distribution : external/public posting : none

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